Semiconductor manufacture includes various test procedures wherein the integrated circuits on semiconductor components are evaluated. One such test, known as burn-in, subjects the components to elevated temperatures, while test signals are applied to the integrated circuits contained on the components. Typically, burn-in testing is performed on individual packaged semiconductor components, which are connected in parallel on a burn-in board having individual sockets for the components. The burn-in board is designed for placement in a burn-in oven in electrical communication with test circuitry of a host controller. The test circuitry is designed to apply test signals which electrically “exercise” the integrated circuits. The components being tested are sometimes referred to as the devices under test (DUTs).
Semiconductor components can also be tested using carriers which function as temporary packages for singulated components, such as dice and chip scale packages. For example, burn-in testing of unpackaged dice can be used to certify the dice as known good dice (KGD). U.S. Pat. No. 5,796,264 to Farnworth et al. entitled “Apparatus For Manufacturing Known Good Semiconductor Dice” discloses a system for burn-in testing unpackaged dice. U.S. Pat. No. 5,519,332 to Wood et al., entitled “Carrier For Testing An Unpackaged Semiconductor Die” discloses an exemplary burn-in carrier for singulated dice. Both of these issued patents are assigned to the assignee of the present application, Micron Technology Inc. of Boise Id. This type of carrier includes an interconnect having test contacts configured to make temporary electrical connections with device contacts on the device under test (DUT). Later generation carriers are configured for burn-in testing chip scale packages having device contacts in the form of terminal contacts, such as solder balls, in an area array.
Rather than being performed on individual components, burn-in testing can also be performed at the wafer-level wherein multiple components, such as dice or packages, are contained on a common substrate, such as a semiconductor wafer. Wafer-level testing of semiconductor components has been practiced since at least 1990, as exemplified by U.S. Pat. No. 5,539,324 to Wood et al., entitled “Universal Wafer Carrier For Wafer-level Die Burn-In”, also assigned to Micron Technology Inc. The '324 patent discloses a carrier for housing a wafer for burn-in testing having contact tips which electrically engage bond pads on the devices under test (DUTs).
Another wafer-level test apparatus is disclosed in U.S. Pat. No. 5,570,032 to Atkins et al., entitled “Wafer Scale Burn-In Apparatus And Process”, also assigned to Micron Technology, Inc. The apparatus in the '032 patent includes a printed circuit board which mates with the wafer under test (WUT), and includes electrically conductive pillars for contacting the bond pads on the devices under test (DUTs). The apparatus also includes heating elements and cooling channels configured to generate the elevated temperatures necessary for burn-in.
A more recent wafer-level burn-in test system is disclosed in U.S. Pat. No. 6,788,094 B2 to Khandros et al., entitled “Wafer-level Burn-in And Test”, assigned to FormFactor Inc. of Livermore, Calif. The system in the '094 patent includes a test substrate that mates with the wafer under test (WUT). Metallic spring contact elements on the test substrate or the wafer, make the individual electrical connections with the devices under test (DUTs).
One important aspect of any wafer-level test system are the individual electrical connections with the contacts on the devices under test (DUTs). A single wafer can include a large number of components (e.g., several hundred dice or packages), and each component can include a large number of device contacts (e.g., 50 to 200 bond pads or terminal contacts) having a small size (e.g., 5 mils or less), and a small pitch (e.g., 10 mils or less). Accordingly, the system must make tens of thousand of separate electrical connections with the wafer.
This requires the test contacts of the test system to be accurately aligned with the device contacts on the devices under test (DUTs) prior to making the electrical connections. In addition, the test contacts are preferably capable of making low resistance (ohmic) electrical connections with the device contacts. For making low resistance connections relatively large forces are sometimes used to bias the test contacts against the device contacts. These large biasing forces can damage the wafer, the test contacts and the device contacts. Spring type contacts are particularly vulnerable to bending and distortion under large contact forces.
To make low resistance electrical connections, the test contacts must also contend with native oxide layers (e.g., AlO2) on the device contacts. These oxide layers have a much higher electrical resistance than the underlying metal of the device contacts. Accordingly, some prior art test contacts include structures for penetrating or scrubbing the device contacts. Again, these penetrating structures can require relatively large contact forces, and can damage the device contacts. The test contacts are also subject to oxidation, and attract contaminants, such as dirt and metal flakes, which can add to the contact resistance.
The present invention is directed to a test method using an interconnect configured to make low resistance electrical connections with components having large numbers of small closely spaced contacts. In addition, the interconnect can be configured to test wafer sized components or die sized components.